Embodiments of the inventive subject matter generally relate to the field of computers, and, more particularly, to a direct current circuit analysis based clock network design.
High-performance very large scale integration (VLSI) chips have an internal clock signal that is a function of an external clock signal. The internal clock signal (hereinafter “clock signal”) is distributed to a large number of clock pins. The clock pins are specific locations or metal shapes on a VLSI chip (hereinafter “chip”) which have a known or estimated effective pin capacitance. The frequency of the clock signal determines the frequency and cycle time of the chip. Shorter cycle times and higher chip frequencies are desirable for improving the chip performance. Clock skew is the difference in arrival time of the clock signal at different locations in the chip. Clock skew can limit achievable cycle time and reduce chip performance. Clock slew is the rate of change of the clock signal voltage.
Clock buffers (hereinafter “sector buffers”) drive the clock signal in a sector (i.e., a section) of the clock distribution network. The sector buffers help in reducing clock skew and improve the chip performance. The output terminal of a sector buffer may be connected at one or more of the multiple locations in the sector. The locations at which the output terminals of the sector buffers are connected, are referred to as sink locations.